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Full text of "1571 Service Manual Preliminary 314002-04 1986 Oct Alt"

^^-^ 



SERVICE MANUAL 

1571 DISK DRIVE 

Preliminary 
OCTOBER 1986 PN-31 4002-04 



n 



Commodore Business Machines, Inc. 

1 200 Wilson Drive, West Chester, Pennsylvania 1 9380 U.S.A. 

Commodore makes no expressed or Implied war- 
ranties with regard to the information contained 
herein. The information is made available solely on 
an as is basis, and the entire risk as to quality and 
accuracy is with the user. Commodore shall not be 
liable for any consequential or incidental damages 
in connection with the use of the information con- 
tained herein. The listing of any available replace- 
ment part herein does not constitute in any case 
a recommendation, warranty or guaranty as to 
quality or suitability of such replacement part. 
Reproduction or use without expressed permission, 
of editorial or pictorial content, in any matter is 
^.^^^ prohibited. 

This manual contains copyrighted and proprietary information. No part 
of this publication may be reproduced, stored in a retrieval system, or 
transmitted in any form or by any means, electronic, mechanical, 
photocopying, recording or otherwise, without the prior written permis- 
sion of Commodore Electronics Limited. 

Copyright © 1986 by Commodore Electronics Limited. 
All rights reserved. 



1S71 SERVICE MANUAL 



/^^, 



TABLE OF CONTENTS 



TITLE PAGE 

SPECIFICATIONS 1 

PRODUCT PARTS LIST 2 

MEMORY MAP 3 

GATE ARRAY CIRCUIT THEORY 4 

GATE ARRAY BLOCK DIAGRAM 6 

IC PIN ASSIGNMENTS 8 

DETAIL PARTS LIST 17 

O BOARD LAYOUT 18 

SCHEMATIC 19 



,0 



1571 SERVICE MANUAL 



^^ 



SPECIFICATIONS 



COMMODORE 1571 



GENERAL FEATURES 



SYSTEM FEATURES 



n 



MEDIA 
CHARACTERISTICS 



INPUTS/OUTPUTS 



POWER REQUIREMENTS 



r) 



DISK DRIVE 



• 5%" Floppy Disk Drive 

• Supports Fast Data Transfer Rates 

• Two Serial Ports for Adding Peripherals 

• Software Disk Format Selectable 

• Comes with Serial and Power Cables 

• Compatible with Commodore 128, Commodore 64, and 
Plus/4 Computers 

• Built-in 6502 Microprocessor 

• 2K RAM 

• 32K ROM 

• Built in DOS 

• Program Load Transfer Rates 

• 300 cps under C64 Control 

• 5200 cps Max under CI 28 Control (Burst Rate) 

• 5200 cps Max under CP/M® Control (Burst Rate) 

• Commodore Standard (GCR) 

• Double Sided/Single Density 

• 350K Storage Capacity (Formatted) 

• Compatible with 1541 Disk Drive 

• Supports Program, Sequential, Relative and User Files 

• CP/M® Compatible (MFM) 

• Single or Double Sided/Double Density Formats 

• Up to 41 OK Storage Capacity (Formatted) 

• Read/Write Compatible with Kaypro,® Osborne,® IBM,® CP/M 86, 
Epson® QX-10 and Numerous Other Formats 

• Supports Most CP/M® Files 

• Two Serial Ports 

• Power Connector 

• 1 17 Volts Ac, 60 Hz, Less than 25 Watts 



Specifications subject to change without notice. 

CP/M is a registered trademarl< of Digital Research, Inc. 

KayPro is a registered trademark of Kaypro, Inc. 

Osborne is a registered trademark of Osborne Computer Corporation. 

IBM is a registered trademark of International Business Machines Corp. 

Epson is a registered trademark of Epson Corporation. 



1571 SERVICE MANUAL 



^ 



PARTS LIST 
1571 



PLEASE NOTE: Commodore part numbers are provided for reference only and do not 
indicate tlie availability of parts from Commodore. Industry standard parts (Resistors, 
Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips. 
Transistors, etc. are available in manual form through the Service Department. Unique or 
non-standard parts will be stocked by Commodore and are indicated on the parts list by a "C". 



TOP CASE ASSY 



Top Case 



C 310508-01 



BOTTOM CASE ASSY 



O 



Bottom Case 


C 310509-01 


PCB Assembly 


C 310420-01 


Power Supply Assembly 


C 250772-01 


Drive Assembly — Newtronics 


C 252083-01 


Drive Assembly — Alps 


C 252092-01 


PCB Shield 


C 252069-01 


PCB Insulation Sheet 


C 252070-01 


FRONT CASE ASSEMBLY 




Front Bezel — Alps 


C 252086-01 


Front Bezel — Newtronics 


C 310507-01 


Disk Eject Lever 


C 252050-01 


LED Assembly 


C 250754-04 


LED Clip 


C 252013-01 


Nameplate 


C 310411-01 


ACCESSORIES 





Users Manual 
Demo Disk 
Power Cord 

6-Pin Din Cable 



C 252095-01 

C 252093-01 

C 252164-01 sub: 

C 903508-04 

C 252159-01 sub: 

C 1540027-01 



n 



1571 SERVICE MANUAL 



r^. 



MEMORY MAP 



./^> 



$FFFF- 
$8000 



$7FFF- 



$4000 



$3FFF- 
$2000 



/- 



y 



\^ 



$1FFF- ^ 

$1800 V 

$17FF- r 

$1000 ^ 

$OFFF- 
$0000 



ROM 



6526 



WD 1770 



6522 (U4) 



6522 (U9) 



RAM' 



/ 



/ 



/ 



CIA 



DISK 
CONTROL 



I/O 



n 



*ONLY 2K OF RAM SPACE AVAILABLE IN THE 1571 

ADDRESS DECODING IS ACCOMPLISHED BY THE 64H157 GATE ARRAY. 



1571 SERVICE MANUAL 



n 



20 PIN GATE ARRAY 
1541B AND 1571 



r^ 



n 



The 20 pin gate array used in the 1541B and 1571 disk drives is designed to work in conjunction 
with the 40/42 pin gate array also used in these drives. As illustrated in the block diagram, this I.C. 
controls 3 operations: 

Address Selector The function of the address selector is to produce ROM, RAM and I/O chip select 
signals by decoding the addresses A10, A12, A13, A14 and A15. The system clocks are not gated 
with the address lines in this I.C. All chip select outputs are ACTIVE LOW. 



Address decode Map: 



RAME 

102 

CS1 

101 

CS2 

ROME 



0000 
1000 
2000 
1800 
4000 
COOO 



- OFFF 

- 1FFF 

- 3FFF 

- 1BFF 

- 7FFF 

- FFFF 



Saddle Canceler This correction signal is generated during the period that the data pattern is two con- 
secutive zeros. With the Commodore GCR type recording format, a problem occurs in the waveform 
of the read signal. In the worst case pattern of 1001 , a saddle condition will occur as illustrated below. 




SADDLE 

-12/AS- 



TRACKS 31-35 



The worst case saddle will occur in tracks 31 to 35 and if not compensated for, will result in a read 
error. In the original 1 541 drives, a one-shot was used to correct the condition; however, in this gate 
array it is corrected digitally. 

The data output line, pin 19, of the R/W Hybrid's data comparitor is fed to the data input line, pin 
3, of this gate array. 

The data is then compared with the last data value which has been latched by the gate array, 2.6/^8 
after the rising or falling edge of the data line. If the current data value differs from the previous data 
value, the clear line is set to a high level for a duration of 63nS. If the values are the same, the clear 
line is not set. 



READ DATA 




2.6 /i 



R/W HYBRID 
PIN 19 



1S71 SERVICE MANUAL 

It takes 2.56 to 2.62ijlS to cancel the saddle. If the saddle should be longer than this length of time, 
the saddle can not be corrected and will result in a read error. Also, if the time for correcting the sad- 
dle is set for a longer time interval, the clear signal will not be set when the data is equal to 1 1 . Therefore, 
approximately 2.6jliS the most suitable time setting for saddle correction. 

Note: The minimum bit rate for tracks 1 — 1 7 is equal to 2.6 /isec. If this time should become less 
due to motor speed, the SYNC signal cannot be recognized on the outer tracks resulting in error. 

Motor Speed Compensator (PLL) 

This gate array detects the motor speed and generates an internal data sampling clock signal that 
matches with the motor speed. (See below) 



n 



READ DATA 



rLTLrLi 



SAMPLING CLOCK 



'V '0' '0' '0' 

SAMPLING DATA 



When the SYNC signal goes to the low level, the LOCK signal goes false and the sampling clock is 
switched to the internal clock signal of the gate array. Once the PLL has sampled the data one's, 
the LOCK signal will go high to indicate that the output of the PLL is valid. If the PLL cannot lock 
on, the internal clock signal will be used and the LOCK signal will remain at the low level. This can 
occur when the stepper is still moving or the spindle motor is not up to speed yet. In short, this allows 
the reading of data independent of motor speed within the lock on limits of the PLL. 



SYNC 



jinnnnnnjirinjuinjiiUL-" 



LOCK 



The 1571 runs on the SYSTEM CLOCK and does not implement the LOCK signal. 



1571 SERVICE MANUAL 



O 



2B1 829 

BLOCK DIAGRAM 

20 PIN GATE ARRAY FOR 1541B/1571 



INPUT 



OUTPUT 



60- 
70 
80- 
90- 
A10 10O- 



A15 
A14 
A13 
A12 



DATA 30 



n 



OSC IQ- 
TEST 4 O 



SYNC 2 O 



1 



ADDRESS 
SELECTOR 



SADDLE 
CANCELER 






MOTOR SPEED 

COMPENSATOR 

(PLL) 



-Ol4 ROME 
-O20 RAME 
-Ol9 10 1 
-Ol8 10 2 
-Ol7 CS 1 
-Ol6 OS 2 



-Oil CLR 



-Ol2 PLL 



-O 13 LOCK 



L 



r^ 



6 



1571 SERVICE MANUAL 



251828 

BLOCK DIAGRAM 

40/42 PIN GATE ARRAY FOR 1541B/1571 



INPUT 



OUTPUT 



YBO- 2-9'^ 
YB7 ^ 



OE 19 O 
SOE 39 0- 



140 



PLL 32 O 
LOCK 33 O 



CLR 31 O 

DSO 150 
16q_ 



DS1 



OSC 21 O 



R/W 34 O 
TED ISO- 
ACCL 20 O 



TEST 1 O 



MTR 13 O 
STPO 12 O 
STP1 1 1 O 



r 



^ 



^ 



-> 



-^ 
-> 






READ 
BLOCK 



X 



WRITE 
BLOCK 



1 



1 



CLOCK 
CIRCUIT 



I 



CPU 
CONTROL 



STEPPER 
DRIVE 



-Ol7 SYNC 



-035 Q 
-036 OX 
-038 B 



-O40 BYTE 
-029 XRW 
-037 CK 



-025 YO 



■0 26 Y1 
-O 27 Y2 
-028 Y3 



-0 24 ATN 



1571 SERVICE MANUAL 



n 



40/42 PIN GATE ARRAY 



PIN ASSIGNMENT 



PIN ASSIGNMENT 



TEST- 
YBO- 
YBl- 
YB2- 
YB3- 
YB4- 
YB5- 
YB6- 
YB7- 
VSS- 

STP1- 

STPO- 

MTR- 

A- 

DSO- 

DS1- 

SYNC- 

TED- 

OE- 

ACCL- 



.'^ 



1 


40 


2 


39 


3 


38 


4 


37 


5 


36 


6 


35 


7 


34 


8 


33 


9 


32 


10 


31 


11 64H156 


30 


12 


29 


13 


28 


14 


27 


15 


26 


16 


25 


17 


24 


18 


23 


19 


22 


20 


21 



■BYTE 

-SOE 

-B 

-CK 

■QX 

■Q 

-RW 

-LOCK 

-PLL 

-CLR 

-VDD 

-XWR 

-Y3 

-Y2 

-Y1 

-YO 

-ATN 

-ATNI 

-ATN A 

-OSC 



TEST- 


1 


42 


YBO- 


2 


41 


YB1- 


3 


40 


YB2- 


4 


39 


YB3- 


5 


38 


YB4- 


6 


37 


YB5- 


7 


36 


YB6- 


8 


35 


YB7- 


9 


34 


VSS- 


10 ^ 


33 


STP1- 


\^ 64H156 


32 


STPO- 


12 


31 


MTR- 


13 


30 


A- 


14 


29 


DSO- 


15 


28 


DS1- 


16 


27 


SYNC- 


17 


26 


TED- 


18 


25 


OE- 


19 


24 


ACCL- 


20 


23 


VCC- 


21 


22 



-BYTE 

-SOE 

-B 

-CK 

-QX 

-Q 

-RW 

-LOCK 

-PLL 

-CLR 

-VDD 

-XWR 

-Y3 

-Y2 

-Y1 

-YO 

-ATN 

-ATNI 

-ATNA 

-OSC 

-GND 



-01 SHOWN 



-02 SHOWN 



n 



40 PIN 

1 

2-9 

10 

11J2 

13 

14 

15,16 

17 

18 

19 

20 

XX 

21 

22 

23 

24 

25-28 

29 

30 

31 

32 

33 

34 

35,36 

37 

38 

39 

40 



42 PIN 

1 

2-9 

10 

11,12 

13 

14 

15,16 

17 

18 

19 

20 

21,22 

23 

24 

25 

26 

27-30 

31 

32 

33 

34 

35 

36 

37,38 

39 

40 

41 

42 



DESC FUNCTION 

TEST Input used in design verification. 

YB0-YB7 Data input/output lines for read/write operation. 

Vss Ground. 

STP0,STP1 Input to stepper driver. 

MTR Control line used to activate the stepper nnotor. 

A Write protect input. Indicates disk is write protected. 

DS0,DS1 Inputs used to produce the binary count for the frequency divide ratio. 

SYNC Sync output. 

TED A low input clears the BYTE line in 2 MHz mode. A high sets 1541 mode. 

OE Input to read/write block to set mode. for Write, 1 for Read. 

ACCL Input select line for the CPU clock. for 1541 - 1 MHz, 1 for 1571 - 2 MHz. 

N/C 

OSC 16 MHz clock input. 

ATNA Attention acknowledge input. 

ATNI Attention line input from serial bus. 

ATN Attention data input from serial bus. 

Y0-Y3 Control output lines for the 4 phases of the stepper motor. 

XRW RAM write enable output. 

Vcc +5VDC. 

CLR High input when the read data is logical 1 . 

P1 1 Input from the 20 pin gate array. Clock compensation. 

LOCK Indicates the PLL LOCK status. When logical 1, PLL is locked. When 0, the 

internal clock is used for sampling data. 

R/W R/W select input. 

Q,Qx Write pulse outputs. 

CK Clock select output - 1 or 2 MHz. 

B Write enable output. 

SOE Enable byte input. 

BYTE Data latched output. 



8 



1571 SERVICE MANUAL 



r^ 



WD1 770/1 772 
5-1/4"FL0PPY DISK CONTROLLER/FORMATTER 



PIN ASSIGNMENT 



n 









cs- 


1 


28 


R/W- 


2 


27 


AO- 


3 


26 


Al- 


4 


25 


DALO- 


5 


24 


DAL1- 


6 


23 


DAL2- 


7 


22 


DAL3- 


8 


21 


DAL4- 


9 


20 


DAL5- 


10 


19 


DAL6- 


11 


18 


DAL7- 


12 


17 


MR- 


13 


16 


GND- 


14 


15 



1 


CS 


CHIP SELECT 


2 


R/W 


READ/WRITE 


3,4 


A0,A1 


ADDRESS 0,1 



n 



5-12 


DAL0-DAL7 


DATA ACCESS 
LINES THRU 7 


13 


MR 


MASTER RESET 


14 


GND 


GROUND 


15 


vcc 


POWER SUPPLY 


16 


STEP 


STEP 


17 


DIRC 


DIRECTION 


18 


CLK 


CLOCK 


19 


RD 


READ DATA 


20 


MO 


MOTOR ON 


21 


WG 


WRITE GATE 


22 


WD 


WRITE DATA 


23 


TROO 


TRACKOO 


24 


IP 


INDEX PULSE 


25 


WPRT 


WRITE PROTECT 


26 


DDEN 


DOUBLE DENSITY 
ENABLE 


27 


DRQ 


DATA REQUEST 


28 


INTRQ 


INTERRUPT 
REQUEST 



-INTRQ 
■ DRQ 
l- DDEN 
-WPRT 

-IP 

-TROO 

-WD 

-WG 

-MO 

-RD 

-CLK 

-DIRC 

-STEP 

-Vcc 



A logic low on this input selects the chip and enable Host communication with the 

device. 

A logic high on this input controls the placement of data on the D0-D7 lines from 

a selected register, while a logic low causes a write operation to a selected register. 

These two inputs select a register to Read/Write data: 

CS A1 AO R/W =1 R/W = 

Status Reg Command Reg 

1 Track Reg Track Reg 

1 Sector Reg Sector Reg 

1 1 Data Reg Data Reg 

Eight bit bidirectional bus used for transfer of data, control, or status. This bus is 
enabled by CS and R/W. Each line will drive one TTL load. 

A logic low pulse on this line resets the device and initializes the status register (in- 
ternal pull-up). 
Ground. 

+ 5V ±5% power supply input. 

The Step output contains a pulse for each step of the drive's RW head. The WD1 770 
and WD 1772 offer different step rates. 

The Direction output is high when stepping in towards the center of the diskette, 
and low when stepping out. 

This input requires a free-running 50% duty cycle clock (for internal timing) at 8 MHZ 
±1%. 

This active low input is the raw data line containing both clock and data pulses from 
the drive. 

Active high output used to enable the spindle motor prior to read, write or stepping 
operations. 

This output is made valid prior to writing on the diskette. 

FM or MFM clock and data pulses are placed on this line to be written on the diskette. 
This active low input informs the WD1 770 that the drive's R/W heads are position- 
ed over Track zero (internal pull-up). 

This active low input Informs the WD1770 when the physical index hole has been 
encountered on the diskette (internal pull-up). 

This input is sampled whenever a Write Command is received. A logic low on this 
line will prevent any Write Command from executing (internal pull-up). 
This input pin selects either single (FM) or double (MFM) density. When DDEN = 0, 
double density is selected (internal pull-up). 

This Active high output indicates that the data register is full (on a READ) or empty 
(on a Write operation). 

This Active high output is set at the completion of any command or reset or read 
of the status register. 



1571 SERVICE MANUAL 



r^ 



6502 MICROPROCESSOR 



1,21 
2 



VSS 
RDY 



3 

4 



</)1 OUT 
IRQ 



PIN ASSIGNMENT 



n) 



n 



vss- 


1 


40 


-RES 


RDY- 


2 


39 


-<A2(0UT) 


</)l(OUT)- 


3 


38 


-S.O. 


IRQ- 


4 


37 


-<j>om) 


N.C.- 


5 


36 


-N.C. 


NMI- 


6 


35 


-N.C. 


SYNC- 


7 


34 


-R/W 


VCC- 


8 


33 


-DO 


1 1 1 1 

O '- CM CO 

<<<< 


9 
10 
11 
12 


32 
6502 31 

/tPRO- 30 

CESSOR 29 


-D1 
-D2 
-D3 
-D4 


A4- 


13 


28 


-D5 


A5- 


14 


27 


-D6 


A6- 


15 


26 


-D7 


A7- 


16 


25 


-A15 


A8- 


17 


24 


-A14 


A9- 


18 


23 


-A13 


A10- 


19 


22 


-A12 


A11- 


20 


21 


-VSS 



NMI 



SYNC 



8 VDD 

9-20 A0-A15 

22,25 

26,33 D0-D7 



34 



37 
38 



39 
40 



R/W 



00 
S.O. 



02 
RES 



DC ground. 

Ready. TTL level input, used to DMA the 
6502. The processor operates normally while 
RDY is high. When RDY makes a transition to 
the low state, the processor will finish the 
operation it is on, and any subsequent opera- 
tion if it is a write cycle. On the next occur- 
rence of read cycle the processor will halt, 
making it possible to tri-state the processor 
to gain complete access to the system bus. 
Phase 1 clock output. 

The Interrupt Request input is a request that 
the processor initiate an interrupt sequence. 
The processor will complete execution of the 
current instruction before recognizing the re- 
quest. At that time, the interrupt mask in the 
Status Code Register will be examined. If the 
interrupt mask is not set, the processor will 
begin an interrupt sequence. The Program 
Counter and the Processor status register will 
be stored on the stack and the interrupt 
disable flag is set so that no other interrupts 
can occur. The processor will then load the 
program counter from the memory location 
$FFFE and $FFFF. 

The Non-Maskable Interrupt Request is a 
negative-edge sensitive request that the pro- 
cessor initiate an interrupt sequence. The pro- 
cessor will complete execution of the current 
instruction before recognizing the request. 
The SYNC output is used in conjunction with 
RDY to allow single instruction execution. 
5VDC input. 

Address bus outputs. Unidirectional bus 
used to address memory and I/O devices. 
Bi-directional bus for transferring data to and 
from the device and the peripherals. 
The read/write line is a TTL level output from 
the processor to control the direction of data 
transfer between the processor and memory, 
peripherals, etc. This line is high for reading 
memory and low for writing. 
Phase clock input. 

Set Overflow flag. A negative going edge 
sets the overflow bit in the status code 
register. 

Phase 2 clock output. 

The Reset input is used to reset or start the 
/^processor from a power down condition. 
During the time that this line is held low, 
writing to or from the /^processor is inhibited. 
When a positive edge is detected on the in- 
put, the jtiprocessor will immediately begin 
the reset sequence. After a system initialisa- 
tion time of 6 cycles, the mask interrupt flag 
will be set and the processor will load the 
program counter from the contents of the 
memory locations $FFFC and $FFFD. This is 
the start location for program control. After 
Vcc reaches 4.75 volts in a power up 
routine, reset must be held low for at least 2 
cycles. At this time the R/W line will become 
valid. 



10 



1571 SERVICE MANUAL 



r^ 



6522 
VERSATILE INTERFACE ADAPTOR (VIA) 



PIN ASSIGNMENT 



r\ 



vss- 

PAO- 
PA1- 
PA2- 
PA3- 
PA4- 
PA5- 
PA6- 
PA7- 
PBO- 
PBl- 
PB2- 
PB3- 
PB4- 
PB5- 
PB6- 
PB7- 
CB1- 
CB2- 

vcc- 



1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 



6522 
VIA 



40 


-CA1 


39 


-CA2 


38 


-RSO 


37 


-RSI 


36 


-RS2 


35 


-RS3 


34 


-RES 


33 


-DO 


32 


-D1 


31 


-D2 


30 


-D3 


29 


-D4 


28 


-D5 


27 


-D6 


26 


-D7 


25 


-<t>2 


24 


-CS1 


23 
22 
21 


-CS2 
-R/W 
-IRQ 



1 


vss 


Ground. 


2-9 


PA0-PA7 


Peripheral I/O Port A. 


10-17 


PB0-PB7 


Peripheral I/O Port B. 


18,19 


CB1, CB2 


Peripheral B Control Lines. 


20 


VCC 


-H5VDC. 


21 


IRQ 


Interrupt Request. 


22 


R/W 


Read/Write. 


23,24 


CS1, CS2 


Chip Select. 


25 


<t>2 


Phase 2 Internal Clock. 


26-33 


D0-D7 


Data Bus 


34 


RES 


Reset Input, Low Active. 


35-38 


RS0-RS3 


Register Select Inputs. 


39,40 


CA1, CA2 


Peripheral A Control Lines 



n 



11 



7577 SERVICE MANUAL 



n 



T520 
VOLTAGE DETECTOR I.C. 



PIN CONFIGURATION 



EQUIVALENT CIRCUIT 






BOTTOM VIEW 



=^ 



6526/8520 
COMPLEX INTERFACE ADAPTOR 



PIN ASSIGNMENT 



vss- 


1 




40 


PAO- 


2 




39 


PA1- 


3 




38 


PA2- 


4 




37 


PA3- 


5 




36 


PA4- 


6 




35 


PA5- 


7 




34 


PA6- 


8 


6526/ 


33 


PA7- 


9 


8520 


32 


PBO- 


10 


CIA 


31 


PB1- 


11 




30 


PB2- 


12 




29 


PB3- 


13 




28 


PB4- 


14 




27 


PB5- 


15 




26 


PB6- 


16 




25 


PB7- 


17 




24 


PC- 


18 




23 


TOD- 


19 




22 


VCC- 


20 




21 





1 
2-9 


VSS 
PA0-PA7 


CNT 


10-17 


PB0-PB7 


SP 


18 


PC 


RSO 
RSI 


19 


TOD 


RS2 
RS3 
RES 


20 
21 
22 


VCC 
IRQ 

R/W 


DBO 
DB1 


23 


CS 


DB2 
DB3 


24 


FLAG 


DB4 

DB5 

DB6 

DB7 

02 

FLAG 


25 

26-33 
34 
35-38 


<t>2 

DB0-DB7 
RES 
RS0-RS3 


CS 

R/W 

IRQ 


39 


SP 



40 



CNT 



n 



Ground Connection. 

Parallel port A signals. Bidirectional parallel 
port. 

Parallel port B signals. Bidirectional parallel 
port. 

Handshake output. A low pulse is generated 
after a read or write on port B. 
Time of day clock input. Programmable 50hz 
or 60hz input. 
5VDC input. 

Interrupt output to microprocessor. 
READ/WRITE input from microprocessor's 
R/W output. 

Chip select input. A low pulse will activate 
CIA. 

Negative-edge sensitive interrupt input. Can 
be used as a handshake line for either parallel 
port. 

02 clock input. 
Bidirectional data bus. 
Low active reset input. Initializes CIA. 
Register select inputs. Used to select all inter- 
nal registers for communications with the 
parallel ports, time of day clock, and serial 
port (SP). 

Serial Port bidirectional connection. An inter- 
nal shift register converts microprocessor 
parallel data into serial data, and visa-versa. 
Count input. Internal timers can count pulses 
applied to this input. It is used for frequency 
dependent operations. 



12 



1571 SERVICE MANUAL 



r^ 



23256 
32K X 8 ROIVI 



PIN ASSIGNMENT 



VPP- 


1 




28 


-VCC 


A12- 


2 




27 


-A14 


A7- 


3 




26 


-A13 


A6- 


4 




25 


-A8 


A5- 


5 




24 


-A9 


A4- 


6 




23 


-All 


A3- 


7 


23256 


22 


-CSi,CE 


A2- 


8 


ROM 


21 


-A10 


A1- 


9 




20 


-CS2 


AO- 


10 




19 


-D7 


DO- 


11 




18 


-D6 


D1- 


12 




17 


-D5 


D2- 


13 




16 


-D4 


GND- 


14 




15 


-D3 



1 


VPP 


5VDC. 


2-10, 






21, 


A0-A14 


Address Bus Inputs 


23-27 






11-13, 
15-19 


D0-D7 


Data Outputs. 


14 


GND 


Ground. 


20 


CS2 


Chip Select. 


22 


CSi, CE 


Output Enable. 


28 


VCC 


5VDC Input. 



'^ 



2016 
2K X 8 STATIC RAM 



PIN ASSIGNMENT 



A7- 

A6- 

A5- 

A4- 

A3- 

A2- 

Al- 

Ao- 

l/Oo- 

l/Oi- 

1/02- 

vss- 



1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 



2016 
RAM 



24 


-VCC 


23 


-A8 


22 


-A9 


21 


-WE 


20 


-OE 


19 


-AlO 


18 


-CS 


17 


-I/O7 


16 


-1/06 


15 


-I/O5 


14 


-I/O4 


13 


-I/O3 



1-8, 






19, 22 


A0-A10 


Address Bus Inputs. 


23 






9-11, 


I/O0-I/O7 


Common Data Input/Output Lines 


13-17 






12 


vss 


Ground. 


18 


CS 


Chip Select Enable, Low Active. 


20 


OE 


Output Enable, Low Active. 


21 


WE 


Write (Input) Enable, Low Active. 


24 


vcc 


5VDC Input. 



A10O- 



A30- 
A06- 



Functional Diagram 



ROW 
DEC. 



MEMORY MATRIX 
128 X 16 X 8 



■Ovcc 



-O V88 



I/O GATE « COL. DEC. 



n 



OEO- 
WEO- 



IcEB 

cfo — r>o — or;> — [ciB> 



A ••■ A 



l/Oo 



I/O7 



13 



n 



7577 SERVICE MANUAL 



COMMON I.C/S 
PIN ASSIGNMENTS AND LOGIC 



7406 

HEX INVERTER BUFFER/DRIVER (OPEN COLLECTOR) 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 





INPUT 


OUTPUT 


A 


Y 


H 

L 


L 
H 



H = HIGH voltage level 
L = LOW voltage level 



7407 

HEX BUFFER/DRIVER (OPEN COLLECTOR) 



PIN ASSIGNMENT 



r) 



u 
[I 

CE 
E 

QND [T 



-r^ 1—1] 

-T^* I ]o] 



I— n 



LOGIC DIAGRAM 

AK. Y 



TRUTH TABLE 




INPUT 


OUTPUT 


A 


Y 


H 

L 


H 
L 



H = HIGH voltage level 
L = LOW voltage level 



7414 • 74LS14 • 74F14 

HEX INVERTER SCHMITT TRIGGER 



n 



PIN ASSIGNMENT 



m vcc 



LOGIC DIAGRAM 



TRUTH TABLE 





5-^>o^. 




INPUT 


OUTPUT 


A 


Y 



1 


1 




H = HIGH voltage level 
L = LOW voltage level 



14 



n 



7432 • 74S32 • 74LS32 • 74F32 
QUAD 2-INPUT OR GATE 



1571 SERVICE MANUAL 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 




JiJvcc 




INPUTS 


OUTPUT 


A 


B 


Y 


L 
L 
H 
H 


L 
H 
L 
H 


L 
H 
H 
H 



Hs HIGH voltage level 
L s LOW voltage level 



7474 • 74S74 • 74LS74 • 74F74 

DUAL D-TYPE FLIP FLOP (POSITIVE EDGE TRIGGERED) 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



O 





OPERATING MODE 


INPUTS 


OUTPUTS 


Sd 


Rd 


OP 


D 


Q 


Q 


Asynchronous Set 
Asynchronous Reset 

(Clear) 
Undetermined*^' 
Load "1" (Set) 
Load "0" (Reset) 


L 
H 

L 
H 
H 


H 

L 

L 
H 
H 


X 
X 

X 

1 
1 


X 
X 

X 

h 
1 


H 
L 

H 
H 

L 


L 
H 

H 

L 
H 



H = HIGH voltage level steady state. 

h = HIGH voltage level one setup time prior to the LGWto-HIGH clock transition. 
L = LOW voltage level steady state. 

I = LOW voltage level one setup time prior to the LOW-toHIGH clock transition. 
X = Dont care. 

t = LGW-to-HIGH clock transition. 
NOTE 

(a) Both outputs will be HIGH while both Sq and Rq are LOW. but the output states 
are unpredictable if Sq and Rq go HIGH simultaneously. 



74123 • 74LS123 

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



n 




— Cextl I Re) 



Ce xtl I Rex t/ Cextl 



JCexiglRexl/ Cext2 
02 , 



— Cext2|Re» 

RD2 [ T 



Q2 



12 



INPUTS 


OUTPUTS 


Rd 


A 


B 


Q 


Q 


L 


X 


X 


L 


H 


X 


H 


X 


L 


H 


X 


X 


L 


L 


H 


H 


L 


! 


J~~L 


"LJ" 


H 


i 


H 


_n. 


H-J" 


t 


L 


H 


J"^ 


T_r 



H = HIGH voltage level 
L = LOW voltage level 
X = Don't care 
t = LOW-to-HIGH transition 
J = HlGH-to-LOW transition 



_rL = One HIGH-level pulse 
"L_r = One LOW-level pulse 



15 



1571 SERVICE MANUAL 



n 



74175 • 74LS175 • 74F175 
QUAD D-TYPE FLIP FLOP 



PIN ASSIGNMENT 



srR[T 




iUvcc 


QoE 




HQ3 


QoU 




13 Q3 


Do [I 




JI]D3 


DiCE 




I3D2 


QiCl 




T3Q2 


Old 




lo]Q2 


QND|T 




T]CP 



(SIR 



1(1) |(B) 



Do 
(4) 



D Q 
-0|>CP 

,.0 



LOGIC DIAGRAM 



02 

(12) 



(2) 

Qo Qo 



Qi Qi 



TRUTH TABLE 



X 



D3 

(13) 



Vcc-P>n16 
QND-Pln8 
( ) ■ Pin number 



Q 

■<:>cp 



«0* 



02 02 



(14) 
O3 O3 



OPERATING MODE 


INPUTS 


OUTPUTS 


MR 


CP 


D„ 


Qn 


On 


Reset (clear) 


L 


X 


X 


L 


H 


Load "1" 


H 


1 


h 


H 


L 


Load "0" 


H 


t 


1 


L 


H 



H = HIGH voltage level steady state. 

h = HIGH voltage level one setup time prior to the LOW- 

to-HIGH clock transition. 
L = LOW voltage level steady state. 
I = LOW voltage level one setup time prior to the LOW- 

to-HIGH clock transition. 
X = Don't care. 
I = LOW-to-HIGH clock transition. 



74LS241 • 74F241 

OCTAL BUFFER, TRI-STATE 

PIN ASSIGNMENT 



■■od 

YbOd 

1*1 [£ 
VbiE 
1(2 [£ 

Yb2[I 
••3 
YbsS 

QNoOfi 






^ 



\ 



"^ 



^Vcc 

HOEb 

HYao 

ISlbO 

iSYti 

Ibl 
iilYa2 
Illb2 

i2lY«3 

nibs 



LOGIC DIAGRAM 






^=-fe- 


Y. 




Y, 




J± 



18 



16 



14 



12 




TRUTH TABLE 



INPUTS 


OUTPUTS 


5i. 


la 


OEb 


lb 


Y. 


Yb 


L 


L 


H 


L 


L 


L 


L 


H 


H 


H 


H 


H 


H 


X 


L 


X 


(Z) 


(Z) 



H = HIGH voltage level 
L = LOW voltage level 
X s Don't care 
(Z) s HIGH Impedance (off) state 



74LS266 

QUAD 2-INPUT EXCLUSIVE NOR GATE (OPEN COLLECTOR) 



PIN ASSIGNMENT 



LOGIC DIAGRAM 



TRUTH TABLE 



n 







INPUTS 


OUTPUT 


A 


B 


Y 


L 

L 
H 
H 


L 
H 
L 
H 


H 

L 
L 
H 



H=: HIGH voltage level 
L = LOW voltage level 



16 



1571 SERVICE MANUAL 



n 



PARTS LIST 
PCB ASSEMBLY #310420 



.;^ 



Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore. Industry standard 
parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips. Transistors, etc. are available 
in manual form through the Service Department, order part #314000-01. Unique or non-standard parts will be stocked by Commodore 
and are indicated on the parts list by a "C". Vendor Name and part number have been provided for your convenience in ordering custom 
or unique parts. 



r^ 



INTEGRATED CIRCUITS 


RESISTORS (Continued) 


U1 


6502 CPU 


C 901435-01 


R18, 19 


47 


U2 


23256 ROM 


C 310654-03 


R20 


20K 


U3 


2016 RAM 200 NS 




R21 


4.7K 


U4 


65SC22A VIA 2MHZ CMOS C 31 0653-01 | 


R22 


IK 


U5 


Gate Array 20 Pin 


C 251829-01 


R23 


390 


U6 


Gate Array 40 Pin 


C 251828-01 


R24 


47 


U7 


R/W Hybrid 


C 251853-01 


R25-28 


2K 


U8 


7406 




R29 


4.7K 


U9 


65SC22A VIA 2MHZ 


C 310653-01 


R30 


15K 


U10 


74LS74 




R31 


2K 


U11 


WD 1770-00 Disk Control 


C 310651-01 sub: 


R32 


4.7K 




WD 1772 Disk Control 


C 310651-02 


R33-35 


2.7K 


U12 


74F32 




R36-38 


IK 


U13 


74LS266 




R39 


43K 


U14 


7407 




R40 


4.7K 


U15 
U16 


74LS14 
7406 








CAPACITORS 


U17 
U18 
U19 
U20 


74LS14 

74LS175 

74LS241 

6526A CIA 2MHZ 


C 906108-02 sub: 




CI -20 
C21 
C22, 23 


Ceramic .l/tF 16V 

Electrolytic 10/tF 25V 

Ceramic -VF 16V 

NPO lOOpF 50V +/-5% 

Ceramic .l/tF 16V 

Elect 47/iF 10V +50%, -10% 

Electrolytic lO/tF 25V 


U21 
U22 


8520 CIA 2MHZ 

PST 520C/D Volt Detector 

74LS123 


C 318029-02 
C 252034-02 


C24 
C27 
C28 
C29 








TRANSISTC 


)RS 




C31 
C32 


Electrolytic l/iF 16V 
Ceramic .OI/iF 50V 








Q1 


MPSU51 PNP 




C33 


Tantalium VF 35V +/-10% 


Q2,3 
Q4 


2SC1815NPN 
2SA673 PNP 








MISCELLANEOUS 


Q5 


2SC945 NPN sub: 
2SC1685R,S 






EMI 1-4 


Ferrlte Bead 


Q7 


2SC1815NPN 




FBI -7 
LI 


Ferrite Bead 

Coil Inductor 2.2/iH 








DIODES 






L3 
RP1 


Coil Inductor lOO/iH 
Resistor Pack IK, lOPIn 








CR3-8 


Signal 1N914 




SW1 


4 Pos Dip Switch C 252144-02 


CR10 


Signal 1N4002 




Y1 


Crystal Module 16MHZ C 325566-01 


CR11 


Zener 3.3V 








CONNECTORS 


RESISTORS 


All ^^mm.^1^ .tfh..«»>aL»..«h.BM. ^ 1 Ji ■■ , rn j li 


5% unless noted 


— All are carbon 1/4 watt. 


CN1 


Header Assy, 4Pin (Molex 3022-04A, AMP 6400984) 








R1-3 


47 




CN2 


Header Assy, Dual RT Angle lOPin 


R4 


4.7K 




CN3 


Header Assy, SPin (Molex 3022^3A, AMP 640098-3) 


R5 


390 1/2W +/-5% 




CN4 


Header Assy, 10Pin (Molex 3022-1 OA, AMP 1-640098-0) 


R6 


1.2K 




CN5 


Header Assy, SPin (Molex 3022-O6A, AMP 640098-6) 


R7, 8 


IK 




CN6, 8 


Connector, 6Pin Din, Shielded C2521 66-01 


R9-11 


47K 




CN7 


Header Assy, SPin (Molex 3022-03A, AMP 640098-3) 


R12 


150 








R13 


390 








R14, 15 


2.7K 








R16, 17 


4.7K 









17 



1571 SERVICE MANUAL 



n 



PCB ASSEMBLY #310420 
BOARD LAYOUT 



1571 DISK Z~^ 



(^ 



rB3 -Q- 




- CD CPO O 



CN2 



Q4 



C5 



05 



R8 -I \- 

R7 -H 1- 



C7 



CZ) 



C19 ^ ^ ^C12 ^ 



R2 
RS" 

C2 



^3- 



R23 



CN3 1 c^a 



R29 

HIZ 



^"" i -j ^Pfe. Z C2U C29+ 



:^R13 



KID C 

CIS 



-,R39 

"V24 CRIS Ql 

C17 



oo 



C16 C32 C17 

CID (ZD CD 



R37 
-I R24 



> 



R14 



U18 



U12 



U18 



HZZD- R18 

4Zh (] 



FB6 



-CZh 



-O' 



R9 

R12 

Rll 

R31 

FBI 



Rl 



Q7^ 



U17 



R15 



n 




rB2 



^> cfb 



c:5' 



U4 



C19' 
U19 



C4 ^ 



Ul 
U2 



U28 
U3 



JC2 



( )C3 



R28 - r k 

R27 -4 I- 



R25 
R26 



18